1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array in which bit lines are hierarchized.
2. Description of Related Art
In recent years, miniaturization and shrinking of semiconductor devices such as DRAM have advanced with a change in generation of manufacturing processes. In order to achieve both the miniaturization and shrinking thereof, a configuration in which bit lines are hierarchized can be employed. For example, Patent Reference 1 discloses a memory cell array in which bit lines having an open bit line structure are hierarchized. Further, for example, Patent Reference 2 discloses a control method of hierarchical switches of a memory cell array having a hierarchical bit line structure.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2011-034614 (U.S. Pat. No. 8,248,834) [Patent Reference 2] Japanese Patent Application Laid-open No. 2007-287209 (U.S. Pat. No. 7,460,388) In a read or write operation of an above-described conventional hierarchical memory cell array, a hierarchical switch in an access path of a selected memory cell is switched to an ON-state first so that a local bit line is connected to a global bit line, and other hierarchical switches are switched to an OFF-state. Thereby, non-selected local bit lines are disconnected from the global bit line, and the selected memory cell can be accessed in a state where bit line capacitance is substantially lowered. Further, in a precharge operation, all hierarchical switches are switched to an OFF-state in order to prepare a subsequent access.
However, the above control requires the hierarchical switch in the access path to be switched from the OFF-state to the ON-state when accessing the selected memory cell. Therefore, noise generated due to the switching increases the potential of the global bit line, which causes a problem that sensing margin of a sense amplifier deteriorates. Further, since the sense amplifier has a differential type configuration, it is possible to cancel the noise viewed from the sense amplifier by controlling the hierarchical switch so as to add in-phase noise to a complementary global bit line (see FIGS. 6 and 7). However, when applying such control, consumption current increases due to an increased number of switching controls to turn on/off the hierarchical switch, and it is inevitable that the sensing margin deteriorates particularly when reading high-level data since fluctuation in potential of the global bit line remains. Further, there arises a problem that a time (tRP) for transitioning from a precharge operation to an active operation is prolonged due to influence of coupling noise that is caused by the control to switch the hierarchical to the OFF-state in the precharge operation.